1. Field of the Invention
The present invention relates to the field of semiconductor device fabrication, and more specifically to a method and structure for reducing silicide encroachment in an integrated circuit.
2. Discussion of Related Art
Today integrated circuits are made up of literally millions of active and passive devices such as transistors, capacitors, and resistors. In order to improve device performance, low resistance silicide layers are generally formed on electrodes such as gate electrodes and on doped regions such as source/drain regions.
For example, FIG. 1A is an illustration of a portion of a complementary metal oxide semiconductor (CMOS) integrated circuit. Integrated circuit 100 includes a PMOS transistor 102 and an NMOS transistor 104 separated by an isolation region 103. NMOS and PMOS transistor 102 and 104 each include a pair of source/drain regions 106, a polysilicon gate electrode 107, and a gate dielectric layer 101. Insulative sidewall spacers 108 are formed along opposite sidewalls of gate electrode 107 as shown in FIG. 1A. In order to decrease the resistance of gate electrode 107 and source/drain regions 106, low resistance silicide is formed on gate electrode 107 and source/drain regions 106.
One method of forming a low resistance silicide is a self-aligned silicide process known as a SALICIDE process. In such a process, a refractory metal layer 109, such as titanium, tungsten, cobalt, nickel or palladium, is blanket deposited over the substrate and MOS devices 102 and 104 as shown in FIG. 1B. The substrate is then heated to cause a reaction between metal layer 109 and exposed silicon surfaces such as source/drain regions 106 and gate electrode 107 to form a low resistance silicide 110 as shown in FIG. 1C. Locations where no silicon is available for reaction, such as oxide spacers 108 and isolation region 103, metal layer 109 remains unreacted. Unreacted metal 109 can then be etched away leaving silicide only on source/drain regions 106 and on gate electrode 107 as shown in FIG. 1D.
A problem with the above described process is that circuits fabricated with the process are vulnerable to short circuits due to silicide encroachment. That is, during the high temperature anneal used to form silicide layer 110 or during subsequent anneal steps, silicide can diffuse or spill over from polysilicon gate electrode 107 and source/drain regions 106 and form an undesired silicide bridge 112 over sidewall spacers 108 and cause shorting of gate electrode 107 to source/drain region 106. Silicide encroachment is further compounded by silicides, such as nickel silicide (NiSi), which experience silicide volume in creases over the combined volume of the consumed silicon and metal layer. For example, the reaction of nickel and silicon creates a nickel silicide/polysilicon gate electrode layer having an approximately 18% volume increase over the silicon electrode shown in FIG. 1A. As such is shown in FIG. 1C to silicide 110 reaches above spacer 108. Silicide encroachment can also cause short circuits between source/drain regions of adjacent devices which are separated by planar isolation regions. For example, as also shown in FIG. 1E, as isolation regions are made more planar and made more compact (less than 0.4 microns wide), such as with shallow trench isolation (STI), silicide from adjacent transistor source/drain regions 106 can diffuse or spill over isolation region 103 and cause silicide shorts 114 between adjacent devices.
In order to help reduce the potential for silicide shorts between source/drain regions and gate electrodes, polysilicon layer 107 is formed thick, (i.e., greater than 2000 xc3x85), in order to ensure that silicide 110 has a large distance to bridge over spacers 108. Unfortunately, however, by increasing the thickness of polysilicon gate 107, the ion implantation technique used to dope gate electrode 107 (typically the source/drain implantation) is unable to drive dopants sufficiently deep into the electrode 107 to provide a uniformly doped low conductivity gate electrode. When the lower portion (portion near gate dielectric layer 101) of the gate electrode has no or reduced doping, the device has increased gate resistance which detrimentally affects the drive current. This non uniform gate electrode doping is commonly referred to as xe2x80x9cpolysilicon depletion effectsxe2x80x9d.
Addition ally, in order to prevent silicide encroachment, silicide layer 110 is generally kept thin (i.e., thinner than the thickness of the polysilicon gate electrode). It would be desirable to be able to form silicide layers which are thicker than the polysilicon layer so that lower resistance electrodes can be fabricated and device performance improved.
Thus, what is desired is a device structure and method of fabrication which reduces silicide encroachment as well as poly depletion effects.
In a first embodiment of the present invention, a semiconductor device having a novel spacer structure and its method of fabrication is described. According to the first embodiment a semiconductor device having an electrode with a first thickness is formed. A silicide layer having a second thickness is formed on the electrode. A sidewall spacer formed adjacent to the electrode and has a height which is greater than the sum of the thickness of the electrode and the thickness of the silicide layer. In another embodiment of the present invention, regions of a device which are to receive silicide are etched below the top surface of isolation regions prior to silicide deposition. In this way silicide regions are formed below the top surface of the isolation regions.